c Makefile template

# c makefile template SRC_DIR = src OUTPUT_DIR = output TARGETS = mytest.bin SRCS = $(wildcard $(SRC_DIR)/*.c) DEPS = $(addprefix $(OUTPUT_DIR)/, $(patsubst %.c, %.d, $(notdir $(SRCS)))) OBJS = $(addprefix $(OUTPUT_DIR)/, $(patsubst %.c, %.o, $(notdir $(SRCS)))) CFLAGS = -Wall -O2 RM = rm -f -v .PHONY: all all: $(OUTPUT_DIR)/$(TARGETS) $(OUTPUT_DIR)/%.d: $(SRC_DIR)/%.c $(CC) -MM $(CFLAGS) $< | sed 's,$*\.o[ :]*,$(basename $@).o $@: ,g' > $@; \ echo "compile .d file: $@" -include $(DEPS) $(OUTPUT_DIR)/%.o: $(SRC_DIR)/%.c $(COMPILE.c) $(OUTPUT_OPTION) $<; \ echo "compile .o file: $@" $(OUTPUT_DIR)/$(TARGETS): $(OBJS) $(LINK.o) $(OUTPUT_OPTION) $^; \ echo "compile .bin file: $@ OK!" .PHONY: clean clean: $(RM) output/*; \ echo "clean ok!"


https://blog.csdn.net/thisinnocence/article/details/48946645
https://blog.csdn.net/alpha_love/article/details/62953847